Targeting Low-Latency C++, HFT & Kernel-Bypass

Joshua Dorst.

Ultra-Low-Latency C++ & Quantitative Systems Developer

Operating at the intersection of hardware precision, zero-allocation C++20, and high-dimensional market geometry. Currently a Dual Student in Computer Science at Infineon Technologies (Smart Power Fab Dresden) and studying Algorithmic Mathematics at FernUniversität in Hagen.

C++20 io_uring SQPOLL eBPF / AF_XDP CUDA & PTX Lock-Free SPSC Tensor Decompositions Riemannian Geometry

View 2.33µs T2T Whitepaper ↓

GitHub LinkedIn Email

DEV_ID // 0x4A6F73 OPT_LEVEL: -O3

Joshua Dorst - Ultra-Low-Latency Systems & Quant Engineer

DPG Physics Award '25 Infineon CS

Benchmark Telemetry

Measured Performance Breakdown

BENCHMARK: 98,999 SAMPLES @ 5 GHz

TICK-TO-TRADE (T2T) FINAL STACK

2.33 µs

6,992 Cycles · P99: 2.43 µs (Jitter-Free)

Pure Linux AF_INET TCP loopback via io_uring SQPOLL. Completely eliminates syscall context switches.

CORE SOFTWARE LOGIC L1 CACHE

12 ns

38 CPU Cycles (Median & 99th %)

Zero-copy SBE parsing → in-place L2 book update → branchless IOC order generation. Operates at the CPU instruction limit.

GPU GRAPH ARBITRAGE CUDA PTX

< 35 µs

Across 500+ Asset Vertices

Lock-free CSC pull-model using PTX warp-reductions (__syncthreads_or) for instant negative cycle exit.

// LATENCY COMPARISON: STANDARD TCP vs. DETERMINISTIC ENGINE 2.7x Latency Reduction

Standard Linux TCP (send/recv syscalls) 6.30 µs (Baseline)

Context switches (Ring-3 ↔ Ring-0) + ksoftirqd jitter

This Engine (io_uring SQPOLL loopback) 2.33 µs (-63%)

2.33 µs (Zero Syscalls)

└─ Pure Software Decision Logic 0.012 µs (12 ns)

12 ns

L1-cache resident, branchless

Note: Intercepting socket calls via LD_PRELOAD into UNIX Domain Shared Memory achieved 0.76 µs, but was discarded as a vanity metric: real exchanges route over TCP/UDP network stacks, not local shared memory. This benchmark targets true determinism over the actual Linux network stack.

FEATURED SYSTEM ARCHITECTURE / C++20 & LINUX KERNEL

HFT TCP Loopback Arbitrage Engine

Repository: JoshyDo/HFT-Engine ↗

An ultra-low latency C++20 trading loop designed to push the absolute physical bounds of the standard Linux AF_INET TCP stack. Accomplishes deterministic sub-2.5 µs Tick-to-Trade latency without requiring proprietary kernel-bypass NIC hardware (Solarflare/Mellanox) by eradicating OS context switches via io_uring SQPOLL and CPU core isolation.

// PIPELINE TOPOLOGY

Incoming Market Data Stream AF_INET TCP

Deterministic SBE tick packet arrival over Linux loopback

AF_INET Loopback

io_uring SQPOLL Ring Cores 3 & 5 · Ring-0

• IORING_SETUP_SQPOLL

• Zero syscall context switch

• SINGLE_ISSUER ring

• Zero lock contention

Zero-Copy Ring Buffer

C++20 Hotpath Engine

12 ns / 38 Cycles Core 4

1. Zero-Copy SBE parsing directly from buffer

2. O(1) in-place L2 limit order book update

3. Branchless IOC order generation (SIMD)

Outgoing IOC Order

Mock Exchange Gateway Core 2

+------------------------------------------------+
|        INCOMING SBE MARKET DATA STREAM         |
+------------------------------------------------+
                       |
                       v  (AF_INET Loopback)
+------------------------------------------------+
| io_uring SQPOLL Ring (IORING_SETUP_SQPOLL)     |
| - Offloads syscalls to Kernel Ring-0 thread    |
| - Lock-free SINGLE_ISSUER ring buffer          |
+------------------------------------------------+
                       |
                       v  Zero-Copy Buffer
+------------------------------------------------+
| C++20 Hotpath Engine  [ 12 ns / 38 cyc ]       |
| - Zero-Copy Simple Binary Encoding (SBE)       |
| - O(1) In-Place L2 Limit Order Book            |
| - Branchless IOC Order Struct Generation       |
+------------------------------------------------+
                       |
                       v  Outgoing Order
+------------------------------------------------+
| Mock Exchange Gateway [ Sub-Microsecond ]      |
+------------------------------------------------+

// CORE ISOLATION & IRQ AFFINITY Zero Contention

CORE 4 C++ Trading Engine _mm_pause

CORE 2 Mock Gateway Isolated

CORE 3/5 io_uring SQPOLL Ring-0

CORE 6 ksoftirqd IRQ Pinning

• Kernel flags: nohz_full=2-6 rcu_nocbs=2-6

• False-sharing prevention: alignas(64) SPSC Ring

// HARDWARE BENCHMARK RESULTS (98,999 Samples) JITTER: 99TH % STRICTLY BOUNDED

← Scroll table horizontally to inspect all percentiles →

Execution Segment	Median Cycles	Median Latency	99th % Cycles	99th % Latency	Optimization Mechanism
Core Logic (Parse → Book → Order)	38 cycles	~12.6 ns	38 cycles	~12.6 ns	Branchless SBE, L1-resident book
Software T2T (Engine + SQPOLL submit)	6,992 cycles	~2.33 µs	7,296 cycles	~2.43 µs	io_uring SQPOLL, zero context switch
Standard Linux TCP (Baseline)	~18,900 cycles	~6.30 µs	> 35,000 cycles	> 11.5 µs	Syscall trap overhead, scheduler jitter

QUANTITATIVE ALGORITHMS & MATHEMATICAL MODELING / MARKET MICROSTRUCTURE

Differential Geometry & High-Dimensional Tensors

THEORETICAL FOUNDATION: FERNUNI HAGEN & DPG AWARD

Applying tools from differential geometry, theoretical physics, and multilinear tensor algebra to financial order-flow dynamics. Bridging clean abstract mathematical proofs with hardware-executable micro-kernels.

RIEMANNIAN MANIFOLDS 01

Metric Tensor g_ij in Risk Space

ds^2 = g_{ij}\,dx^i dx^j = \Delta x^T \Sigma^{-1} \Delta x

Standard Euclidean metrics assume a flat market grid. When assets are heavily correlated ( $\rho = 0.9$ ), the market manifold is sharply curved. While Euclidean distance shows identical risk ( $d = 2.12$ ), applying the Riemann Metric Tensor proves Portfolio B carries over 4x higher structural risk ( $d = 6.71$ ).

Application: Non-Euclidean Portfolio Geometry

TENSOR ALGEBRA 02

Contravariant vs. Covariant Dual Spaces

v' = \Lambda v \quad\Big|\quad w' = \Lambda^{-T} w

Standard linear algebra tools (NumPy) treat all 1D arrays identically. But asset allocations ( $v$ ) are contravariant vectors, while Greeks ( $\Delta = \partial V / \partial S$ ) reside in dual space as covariant covectors. Failing to apply dual transformation laws breaks the invariant inner product, causing phantom exposure in delta-neutral hedges.

Application: Basis-Invariant Delta Hedging

HOSVD DECOMPOSITIONS 03

Higher-Order SVD for Microstructure Tensors

\mathcal{X} \approx \mathcal{G} \times_1 U^{(1)} \times_2 U^{(2)} \times_3 U^{(3)}

Decomposing order-book order flow as 3D arrays: Asset × Depth × Time ( $N \times N \times T$ ). Applying Tucker HOSVD condenses noisy queue sizes into low-rank core tensors ( $3 \times 3 \times 2$ ), isolating deterministic cross-venue lead-lag signals ( $\rho = 0.85 \text{ at } \tau = 4$ ) before standard PCA collapses time horizons.

Application: Real-Time Lead-Lag Signal Extraction

SELECTED WORK & OPEN SOURCE / HIGH PERFORMANCE

Engineered for Extreme Throughput

CUDA / C++20 GPU ARBITRAGE

CUDA Multi-Hop Graph Arbitrage

Lock-free Compressed Sparse Column (CSC) pull-model graph engine detecting multi-hop triangular arbitrage across 500+ vertices. Bypasses standard Bellman-Ford using PTX warp-reductions (__syncthreads_or) for immediate negative-cycle early exits under 35µs.

< 35µs Kernel cudaMallocHost PTX Intrinsics

Integrated in HFT-Engine View Source ↗

Swift / AVFoundation PRODUCTION APP

PocketTranscoder (Native iOS Media Processing)

Developed and shipped a production native iOS application for offline, zero-API video-to-audio extraction. Engineered around strict on-device memory management, efficient local file I/O pipelines, and zero third-party cloud data egress.

App Store Published 100% Offline Zero-Heap Bloat

Apple App Store Live App Store ↗

C++ / Python QUANT DEV

Backtest-API Acceleration Engine

High-performance quantitative backtesting suite with SMA crossover strategies and parameter grid-search optimization. Replaced slow vectorized Python loops with a multithreaded C++ execution core, achieving 10-50x speedups across historical ticks.

10-50x Speedup Multithreaded C++ Grid Optimization

Open Source View Source ↗

C# / Netcode DISTRIBUTED

Nebula Multiplayer Network Synchronization

Resolved complex distributed state synchronization bugs for the open-source Nebula multiplayer framework (PR #773). Fixed spatial and ground combat entity desynchronization under high tick rates.

State Desync Fix PR Merged Simulation

NebulaModTeam / PR #773 PR #773 ↗

FOUNDATION & EXPERIENCE / HARDWARE TO PRODUCTION

Semiconductors, Physics & Mathematics

Infineon Technologies

Dual Student — Software Engineering / IT Factory Integration

Jul 2025 – Present · Dresden

Embedded in the Factory Integration department supporting mission-critical 24/7 semiconductor manufacturing systems at Infineon's flagship Smart Power Fab.

Analyzing real-time data flow disruptions between fabrication equipment and MES (Manufacturing Execution System).
Developing automated telemetry and integration solutions to increase production line throughput.
Working in an environment where microsecond data reliability and zero downtime are absolute imperatives.

C++ Python MES Integration Smart Factory 4.0

Academic Track

FernUniversität in Hagen 2026 – Present

Parallel Coursework: Algorithmic Mathematics

Deepening theoretical foundations in abstract algebra, graph algorithms, and multilinear tensor analysis.

DHSN Leipzig 2025 – 2028

Bachelor of Science, Computer Science (Co-op with Infineon)

Systems architecture, low-level operating systems, and distributed networks.

NATIONAL RECOGNITION

DPG Physics Student Award 2025

Deutsche Physikalische Gesellschaft (DPG) · Jan 2025

Awarded for outstanding achievements in physics, academic excellence, and original scientific problem-solving. This honor is reserved for a select few students nationwide with demonstrated mastery in physical modeling.

Engineering Mindset

Mechanical Sympathy

Belief in knowing the exact hardware cache topology, pipeline stages, memory bus limits, and kernel execution paths before writing a single line of production C++.